ML4FE Workshop, University of Hawaii

A general form of HDL-based Neural Network in a digital ASIC

Not scheduled

10m

"Idea" talk (5'+5')

Speaker

Yun-Tsung Lai (KEK IPNS)

Description

This report will present an idea of implementing a general form of Neural Network in a digital ASIC. As High-Level-Synthesis has been a popular approach for ML inference to FPGA, we use HDL to construct a Neural Network into a pure RTL design, where the network is parameterized as a general form. This design is expected to be utilized not only in FPGA but also as a digital ASIC. We will discuss the idea and plan for future application.