Speakers
Description
Integration of machine learning (ML) algorithms within the front-end ASICs used for charge detection and readout in high-energy and nuclear physics experiments can alleviate data transfer bottlenecks to back-end data acquisition systems. By only transmitting higher-level signal features inferred from the front-end signals (such as amplitude, time constant, time of arrival, or even particle types), significant amount of energy and data movement can be saved. However, such extreme edge-AI systems must operate under stringent hardware constraints such as micron-level dimensions, sub-milliwatt power consumption, and nanosecond-scale latency, while providing clear accuracy advantages over traditional architectures. Moreover, it is impractical, if not impossible, to manually determine optimal design and architectural choices for the corresponding artificial neural networks (ANNs) among possibilities that easily exceed billions even for small-scale problems.
To address these challenges, we employ intelligent search using multi-objective Bayesian optimization, integrating both neural network architecture search, variable bit quantization, and logic synthesis in the optimization loop. This approach provides reliable feedback on the collective impact of all cross-domain design choices. We showcase the effectiveness of our approach by finding several Pareto-optimal design choices for effective and efficient ANNs that perform real-time feature extraction from input pulses within the individual pixels of a readout ASIC. The proposed optimization approach was used to realize a smart readout ASIC for segmented radiation detectors. The chip, which was designed in 65 nm CMOS technology, contains 23 independent sensing channels. Each channel features a low-noise analog front-end, single-ended to differential converter, ADC driver, high-speed 12-bit ADC, digital signal processor (DSP), and two-layer ANN with on-chip weights for performing regression or classification tasks. The DSP was realized using a high-level synthesis design flow. Each channel contains 1.8 kb of on-chip memory and consumes approximately 14.3 mW at the nominal sampling rate of 25 MS/s.